pastermil@sh.itjust.works to Programmer Humor@lemmy.ml · 6 months agoSome Mnemonicssh.itjust.worksimagemessage-square3fedilinkarrow-up11
arrow-up11imageSome Mnemonicssh.itjust.workspastermil@sh.itjust.works to Programmer Humor@lemmy.ml · 6 months agomessage-square3fedilink
minus-square9point6@lemmy.worldlinkfedilinkarrow-up0·6 months agoI still don’t know why this architecture went for a Double XOR as the NOP, I guess they were just flexing that the reference chip design could do both in a single cycle
minus-squarepancake@lemmygrad.mllinkfedilinkarrow-up1·edit-26 days agoThis content will be automatically deleted
I still don’t know why this architecture went for a Double XOR as the NOP, I guess they were just flexing that the reference chip design could do both in a single cycle
This content will be automatically deleted