A Reddit Refugee. Zero ragrets.

Engineer, permanent pirate, lover of all things mechanical and on wheels

moved here from lemmy.one because there are no active admins on that instance.

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Joined 1 year ago
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Cake day: December 22nd, 2023

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  • The single CCD cache stack was a huge problem with the original x3d dual ccd chips (7900/12coreand 7950/16core) as OS’es were not “ccd aware” about which chiplet has the cache. There is a huge access penalty for cache traversal between chiplets as the data has to travel across the infinity fabric rather than inside the CCD only. When the OS would distribute threads across both ccd’s because it only saw threads, you would never get the full benefit of x3d due to loads being placed on cores without x3d and incurring the traversal penalty. This has largely been fixed in Windows and Linux by now, but it still limits the true potential of the non-x3d ccd.

    Dual cache stacks would allow both CCD’s to utilize the full benefits of a massive cache rather than just one.


  • This applies to human behavior on this medium, not the machines and services themselves.

    I’d argue thr machines behave this way somewhat similarly too. The Internet’s services are designed around resiliency first and foremost, what with how IP packet routing is designed for “Any Possible Path” between end points. Any path that becomes “damaged” or otherwise closed is often circumvented if another link exists in the network.
    The only way to truely restrict and censor internet data is to control 100% of the data paths into a certain geographical area and inspect every single bit passing through them, which is a monumental task.